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NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable
Description
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The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential ECL/PECL and they are selected by the CLK_SEL pin. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE) is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 4). The NB100LVEP224 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output, the same bias and termination scheme is required. Unused output pairs should be left unterminated (open) to "reduce power and switching noise as much as possible." Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. The wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels. The NB100LVEP224, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP224 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single-ended CLK input operation is limited to a VCC 3.0 V in LVPECL mode, or VEE -3.0 V in NECL mode. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D.
Features
LQFP-64 FA SUFFIX CASE 848G A WL YY WW G
NB100 LVEP224 AWLYYWWG
64 1
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
* * * * * *
20 ps Typical Output-to-Output Skew 75 ps Typical Device-to-Device Skew Maximum Frequency > 1 GHz 650 ps Typical Propagation Delay LVPECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
* * * * *
Internal Input Pulldown Resistors Q Output will Default Low with Inputs Open or at VEE Thermally Enhanced 64-Lead LQFP CLOCK Inputs are LVDS-Compatible; Requires External 100 W LVDS Termination Resistor Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 7
1
Publication Order Number: NB100LVEP224/D
NB100LVEP224
Q10 Q10 Q12 Q12 Q13 Q13 Q14 Q14 34
Q11
Q11
VEE
VCCO Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 VCCO
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
47
46
45
44
43
42
41
40
39
38
37
36
35
VEE 33 32 31 30 29 28 27 26 25
Q8
Q8
Q9
Q9
VCCO Q15 Q15 Q16 Q16 Q17 Q17 Q18 Q18 Q19 Q19 Q20 Q20 Q21 Q21 VCCO
NB100LVEP224
24 23 22 21 20 19 18 17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCCO
CLK0
CLK1
CLK0
CLK1
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transferring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 64-Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION
PIN CLK0*, CLK0** CLK1*, CLK1** CLK_SEL* OE* Q0-Q23, Q0-Q23 VCC, VCCO VEE*** FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Input CLK Select ECL Output Enable ECL Differential Outputs Positive Supply Negative Supply
CLK_SEL
Table 2. FUNCTION TABLE
OE (1) L L H H CLK_SEL L H L H Q0-Q23 CLK0 CLK1 L L Q0-Q23 CLK0 CLK1 H H
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally.
1. The OE (Output Enable) signal is synchronized with the falling edge of the LVPECL_CLK signal.
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VCCO
VCC
Q23
Q23
Q0
Q0
VEE
Q22
Q22
OE
NB100LVEP224
CLK_SEL CLK0 CLK0 CLK1 VCC VEE CLK1 OE D
0 24 24 1 Q Q0-Q23 Q0-Q23
Figure 2. Logic Diagram
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 Value 75 kW 37.5 kW > 2 kV > 150 V > 2 kV Pb-Free Pkg Level 3
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) LQFP-64 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, refer to Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 654 Devices
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (See Application Information) Thermal Resistance (Junction-to-Case) (See Application Information) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 0 lfpm 500 lfpm 64 LQFP 64 LQFP 64 LQFP 64 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VI VCC VI VEE Condition 2 Rating 6 -6 6 to 0 -6 to 0 -40 to +85 -65 to +150 35.6 30 3.2 6.4 265 265 Unit V V V C C C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NB100LVEP224
Table 5. LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) (Note 5) Input LOW Voltage (Single-Ended) (Note 5) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) CLK/CLK Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 130 1355 555 1335 555 Typ 160 1480 680 Max 195 1605 900 1620 900 Min 135 1355 555 1335 555 25C Typ 165 1480 680 Max 200 1605 900 1620 900 Min 140 1355 555 1275 555 85C Typ 165 1480 680 Max 205 1605 900 1620 900 Unit mA mV mV mV mV
1.2
2.5 150
1.2
2.5 150
1.2
2.5 150
V mA mA
IIH IIL
0.5 -150
0.5 -150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V. 4. All outputs loaded with 50 W to VCC - 2.0 V. 5. Do not use VBB at VCC < 3.0 V. 6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) (Note 9) Input LOW Voltage (Single-Ended) (Note 9) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 140 2155 1355 2135 1355 1.2 Typ 165 2280 1480 Max 195 2405 1700 2420 1700 3.3 Min 145 2155 1355 2135 1355 1.2 25C Typ 175 2280 1480 Max 205 2405 1700 2420 1700 3.3 Min 145 2155 1355 2135 1355 1.2 85C Typ 175 2280 1480 Max 210 2405 1700 2420 1700 3.3 Unit mA mV mV mV mV V
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V. 8. All outputs loaded with 50 W to VCC - 2.0 V. 9. Single ended input operation is limited VCC 3.0 V in LVPECL mode. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP224
Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current VEE = -2.5 V VEE = -3.3 V Min 130 140 -1145 -1945 -1165 -1945 VEE + 1.2 Typ 160 165 -1020 -1820 Max 195 195 -895 -1600 -880 -1600 0.0 Min 135 145 -1145 -1945 -1165 -1945 VEE + 1.2 25C Typ 165 175 -1020 -1820 Max 200 205 -895 -1600 -880 -1600 0.0 Min 140 145 -1145 -1945 -1165 -1945 VEE + 1.2 85C Typ 165 175 -1020 -1820 Max 205 210 -895 -1600 -880 -1600 0.0 Unit mA mV mV mV mV V
Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) (Note 13) Input LOW Voltage (Single-Ended) (Note 13) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) (Figure 5) Input HIGH Current Input LOW Current CLK CLK
IIH IIL
150 0.5 -150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. 12. All outputs loaded with 50 W to VCC - 2.0 V. 13. Single ended input operation is limited VEE -3.0 V in NECL mode. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 15)
-405C Symbol VOpp Characteristic Differential Output Voltage (Figure 3) fout < 50 MHz fout < 0.8 GHz fout < 1.0 GHz Min 600 600 600 500 600 Typ 750 750 700 600 700 20 50 1 200 200 200 100 200 300 800 700 800 40 300 5 1200 200 200 200 100 200 300 Max Min 600 600 525 550 650 255C Typ 725 725 650 650 800 20 50 1 800 750 900 40 300 5 1200 200 200 200 150 250 350 Max Min 575 550 400 650 750 855C Typ 700 650 525 750 850 35 100 1 800 1000 1150 60 300 5 1200 Max Unit mV mV mV ps ps ps ps ps mV ps ps ps
tPLH tPHL tskew tJITTER VPP tS tH tr/tf
Propagation Delay (Differential Configuration) CLKx-Qx CLK_SELx-Qx Within-Device Skew (Note 16) Device-to-Device Skew (Note 17) Random Clock Jitter (Figure 3) (RMS) Input Swing (Differential Configuration) (Note 19) (Figure 5) OE Set Up Time (Note 18) OE Hold Time Output Rise/Fall Time (20%-80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC - 2 V. 16. Skew is measured between outputs under identical transitions and conditions on any one device. 17. Device-to-Device skew for identical transitions at identical VCC levels. 18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High-to-Low transition ensures outputs remain disabled during the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock. 19. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
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NB100LVEP224
900 OUTPUT AMPLITUDE (mV) 800 700 600 500 400 300 200 0.5 0.6 0.7 0.8 0.9 1.0 RMS JITTER (ps) 2.5 V 3.3 V Q AMP (mV) 10 9.0 8.0 6.0 5.0 4.0 3.0 2.0 1.0 0 RMS JITTER (ps) 7.0
1.1
1.2
1.3
1.4 1.5
INPUT FREQUENCY (GHz)
Figure 3. Output Amplitude (VOPP) versus Input Frequency and Random Clock Jitter (tJITTER)
CLK
CLK
OE Q
Q
Figure 4. Output Enable (OE) Timing Diagram
VCC(LVPECL) VPP VIHCMR VIH(DIFF) VIL(DIFF) VEE
Figure 5. LVPECL Differential Input Levels
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NB100LVEP224
APPLICATIONS INFORMATION
Using the thermally enhanced package of the NB100LVEP224
The NB100LVEP224 uses a thermally enhanced 64-lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP224 high-speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP224. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP224 applications on multi-layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 6 providing an efficient heat removal path.
All Units mm
supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 7, "Recommended solder mask openings", shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 7. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
All Units mm 0.2 1.0
4.6
0.2
1.0
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
Figure 7. Recommended Solder Mask Openings
4.6
Proper thermal management is critical for reliable system operation. This is especially true for high-fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided:
Table 9. Thermal Resistance *
lfpm 0 qJA 5C/W 35.6 32.8 30.0 qJC 5C/W 3.2 4.9 6.4
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
100 500
Figure 6. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will
* Junction to ambient and Junction to board, four-conductor layer test board (2S2P) per JESD 51-8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP224 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE.
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NB100LVEP224
ORDERING INFORMATION
Device NB100LVEP224FA NB100LVEP224FAG NB100LVEP224FAR2 NB100LVEP224FARG Package LQFP-64 LQFP-64 (Pb-Free) LQFP-64 LQFP-64 (Pb-Free) Shipping 160 Units / Tray 160 Units / Tray 1500 / Tape & Reel 1500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB100LVEP224
PACKAGE DIMENSIONS
LQFP 64 LEAD EXPOSED PAD 848G-02 ISSUE A
M M/2 -Z-
64 1 4 PL
AJ AJ
49 48
0.20 (0.008) T X-Y Z
PLATING
L B/2
16 17 32 33
B
AB
L/2
0.08 (0.003)
A/2 A DETAIL AH -E- -T-
SEATING PLANE
DETAIL AJ-AJ 0.20 (0.008) E X-Y Z
AG G
60 PL
4 PL
G/2
AG
0.08 (0.003) T
D 0.08 (0.003) AE
EXPOSED PAD 16 17
64 PL M
T X-Y
Z
V 0.05 (0.002)
S
32 33
S
C
K AF
W N F H DETAIL AH
1 64 49
48
VIEW AG-AG
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EEEE CCCC EEEE CCCC EEEE
REF M
-X-
-Y-
AA J
D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE BASE DETERMINED AT DATUM PLAND E". METAL 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). 8. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
Y T-U
Z
R AC AD
DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE AF
MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.35 1.45 0.17 0.27 0.45 0.75 0.50 BSC 1.00 REF 0.09 0.20 0.05 0.15 12.00 BSC 12.00 BSC 0.20 --- 0_ 7_ 0_ --- --- 1.60 11 _ 13 _ 11 _ 13 _ 0.17 0.23 0.09 0.16 0.08 --- 0.08 --- 4.50 4.78 4.50 4.78
INCHES MIN MAX 0.394 BSC 0.394 BSC 0.053 0.057 0.007 0.011 0.018 0.030 0.020 BSC 0.039 BSC 0.004 0.008 0.002 0.006 0.472 BSC 0.472 BSC 0.008 --- 0_ 7_ 0_ --- --- 0.063 11 _ 13 _ 11 _ 13 _ 0.007 0.009 0.004 0.006 0.003 --- 0.003 --- 0.180 0.188 0.180 0.188
P
0.25
GAGE PLANE
NB100LVEP224
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB100LVEP224/D

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